Various embodiments of this disclosure relate to exception handling and, more particularly, to sharing program interrupt logic in a multithreaded processor.
With a microprocessor, when instructions execute and hit an exception condition, the processor retries the instruction in slow mode (i.e., a single-step mode of operation), and information about the exception condition is captured in hardware during this slow mode. In some microprocessors, the information is then consumed by a firmware layer (e.g., millicode), and the exception condition is reported to the operating system through the firmware layer.
A straight-forward implementation of multithreading requires exception tracking logic to be implemented multiple times per core, leading to power and area consumption for a piece of logic that is required only infrequently.